DS2404B【PDF 22/29 页】IC ECONORAM TIMECHIP 5.5V 16SSOP

DS2404

29 of 29

20. The reset low time (tRSTL) should be restricted to a maximum of 960μs, to allow interrupt signaling,

otherwise, it could mask or conceal interrupt pulses.

21. When the battery is attached, the oscillator powers up in the off state.

22. The optimal sampling point for the master is as close as possible to the end time of the 15

μs tRDV

period without exceeding tRDV. For the case of a Read-one time slot, this maximizes the amount of

time for the pull-up resistor to recover the line to a high level. For a Read-zero time slot it ensures

that a read will occur before the fastest 1-Wire device(s) release the line (tRELEASE = 0).

23. The duration of the low pulse sent by the master should be a minimum of 1μs with a minimum value

as short as possible to allow time for the pull-up resistor to recover the line to a high level before the

1-Wire device samples in the case of a Write 1 Low Time or before the master samples in the case of

a Read Low Time.

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